1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
Priority is claimed on Japanese Patent Application No. 2010-050855, Mar. 8, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
Improvement in the degree of integration of semiconductor devices has been achieved by miniaturization of transistors. However, the miniaturization of the transistors has almost reached its limit. Further miniaturization beyond its limit can cause short channel effects of transistors which make it difficult for the transistor to operate accurately.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2009-164597 and Japanese Unexamined Patent Application, Second Publication, No. JP-A-2007-48941 disclose that, to solve this problem fundamentally, a method of three-dimensionally forming the transistor by processing a semiconductor substrate in a three-dimensional manner. For example, a vertical transistor has been suggested. The vertical transistor employs, as a channel, a silicon pillar that extends in a direction vertical to a main surface of the semiconductor substrate. The vertical transistor may have advantages such as obtaining a larger drain current due to a small occupied area and complete depletion. The vertical transistor may realize a close-packed layout known as 4F2 (F being the minimum processing size).
In general, a dynamic random access memory (DRAM) includes a plurality of memory cells each of which includes the vertical transistor including the silicon pillar and a capacitor. The vertical transistor has the following configurations. One of impurity diffusion layers such as a source or drain of the vertical transistor is connected to a bit line. The other thereof is connected to the capacitor.
Typically, the capacitor is disposed over the vertical transistor among the capacitor and the vertical transistor which constitute the memory cell. The capacitor is disposed over the silicon pillar. The bit line is disposed below the silicon pillar. Due to this, it is necessary for the bit line to be buried in the semiconductor substrate including the silicon pillars, and the bit line to extend under the alignment of the silicon pillars.